In recent years, due to the growth of portable electronics, there has been a push to decrease the power used by microcontrollers (or “MCU”), microprocessors, application processors and other circuits used in portable electronic appliances. With lower power requirements, effective electronics operation time can be extended, or alternatively, smaller batteries can be used. Commonly, the power consumption of a microcontroller and associated circuits may be reduced by using a lower supply voltage, or by reducing the amount of internal capacitance being charged and discharged during the operation of the circuit.
One method for reducing microcontroller power relies on hardware or software-based power mode switching. Power modes can be selected for microcontroller components or resources based on operating state, operating conditions, and/or sleep cycle characteristics and other factors to configure low power modes for selected microcontroller components at the time the processor enters a low power or sleep state. In some systems, a set of predefined low power configurations can be used, while more sophisticated systems can dynamically select low power configurations to maximize power savings while still meeting system latency requirements.
However, even with available low power modes, microcontroller power usage can be adversely affected by interactions with connected sensors, memory systems, or other peripherals. Frequent interrupts or requests for service from such peripherals can greatly limit the time a microcontroller can remain in a low power mode. Systems that provide a reliable overall power management protocol and components for very low power operation are still needed.
To reduce or mitigate the foregoing described problems, in one embodiment, a low power microcontroller system is provided that can include a processing unit supporting at least one near or sub-Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. The processing unit can include a plurality of cores in some embodiments, with the memory blocks (e.g. an SRAM instance) interconnected to a least one core.
A power control system that includes power gates to power control at least the memory blocks can be connected, as well as a wake-up interrupt controller connected to the power control system. A voltage regulator system including at least one of a buck converter and a LDO can supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. The system also includes a plurality of clocks connected to define clock domains associated with separate power domains. The clocks can be gated by a DMA controller, with clock gate circuits optionally including a latch. In some embodiments, clocks can be used without synchronization (e.g. SRAM clocks)
In such a described system, a first and second transistors respectively having differing Vt can be supported. Stacked transistors can also be used. In other embodiments, the microcontroller system can include always-on circuits (e.g. for a wake-up controller) and the memory blocks can be each connected to at least one voltage regulator. Power savings can be realized by supporting power control system that can sequence power distribution to separate power domains.
In another embodiment, a microcontroller system includes a processing core and a plurality of memory blocks. Always-on circuitry having at least some transistors operating in near-Vt mode for low power operation can be connected to the processing core, and a power control system able to inactivate at least some of the plurality of memory blocks by power gating is provided. Each memory block can be connected to a DMA controller and independently power controlled.
In some embodiments, the always-on circuitry can be connected to timing, voltage, and I/O peripherals, and responds to on-chip interrupts, off-chip requests, or reset circuitry. Alternatively, the always-on circuitry can be activated in response to a counter or timer state. To improve power savings, the always-on circuitry can be in a separate power domain from the core.
In another embodiment, a microcontroller system includes a processing core and a plurality of memory blocks. A DMA system can be connected to the plurality of memory blocks, with the DMA system including a DMA controller. At least two peripherals, with each peripheral having associated logic circuitry can also be connected to the DMA system, with each peripheral and its associated logic circuitry being supported in a distinct power domain.
To improve power performance, in some embodiments, the DMA system can be power gated. The DMA system can also include an arbiter to determine which of the plurality of memory blocks is accessible and use a crossbar to enable communication between the plurality of memory blocks. In some embodiments, peripherals are allowed to access memory independently of the processing unit.
Other power saving features of the microcontroller system are provided by a power control system that includes power gates to power control the plurality of memory blocks. The microcontroller system can include voltage regulator systems for supplying voltage to separate power domains of the at least two power gated peripherals and power gates to power control at least some of the memory blocks. A plurality of clocks can be connected to define clock domains associated with separate power domains of the peripherals.
In another embodiment, a microcontroller system includes at least two processing units operating at respective first or second clock frequencies and each able to make requests for memory access. At least one memory block is connectable to the processing units, and an arbitration circuit can be used to manage memory access requests from the processing units. A clock muxing circuit can apply, in response to arbitration circuit request, the respective first or second clock frequency of the respective processing units to the connected at least one memory block.
In some embodiments, the at least two processing units can operate at respective first or second clock frequencies in distinct power domains. Voltage regulator systems can supply voltage to distinct power domains, and power gating circuitry, including power gating of memory blocks, can also be supported. In some embodiments, the respective first or second clock frequencies are different, while in others the respective first or second clock frequencies are identical and clock phase is different. Commonly, the respective first or second clock frequencies have a small integer ratio relationship.
In another embodiment of a microcontroller system, a processing unit and a plurality of memory blocks are connected to a power gate capable DMA system with the DMA system including a DMA controller. At least two peripherals, with each peripheral having associated logic circuitry connected to the DMA system, are supported in a distinct power domain.
Advantageously, transfer information can be accumulated into the peripherals while the DMA system is power gated. This allows support of a deep-sleep mode wherein the DMA system is power gated while the microcontroller is in deep-sleep mode.
In another embodiment, a microcontroller system includes a processing unit in at least one power domain, with the processing unit having a plurality of transistors with differing Vt to permit various power operational modes. A plurality of memory blocks in at least one power domain is also provided, with each memory block connected to a DMA controller and independently power controlled. A power control system, including power gates, can be used to power control at least the memory blocks. Voltage regulator systems can also be connected to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system.